JournalAnnals of Data Science
Conference · 2026
2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026
Cited by 0
Design and Synthesis of 16-bit FIFO Synchronous Block using…
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Publication details
- Venue
- Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach
- Type
- Conference · 2026
- Citations
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APA
Sagar, R. (2026). 2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026. Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach.
Harvard
Sagar, R. (2026) '2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026', Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach.
IEEE
R. Sagar, "2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026," Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach, 2026.
Vancouver
Sagar R. 2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026. Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach. 2026.
MLA
Sagar, Renuka. "2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026." Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach, 2026.
Chicago
Sagar, R.. "2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026." Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach (2026).
BibTeX
@inproceedings{sagar2026, title={2026 5th International Conference on Distributed Computing and Electrical Circuits and Electronics Icdcece 2026}, author={Sagar, Renuka}, booktitle={Design and Synthesis of 16-bit FIFO Synchronous Block using Physical Design Approach}, year={2026}, }